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PRELIMINARY
CY7C1353G
4-Mbit (256K x 18) Flow-through SRAM with NoBLTM Architecture
Features
* Can support up to 133-MHz bus operations with zero wait states -- Data is transferred on every clock * Pin compatible and functionally equivalent to ZBTTM devices * Internally self-timed output buffer control to eliminate the need to use OE * Registered inputs for flow-through operation * Byte Write capability * 256K x 18 common I/O architecture * 2.5V / 3.3V I/O power supply * Fast clock-to-output times -- 6.5 ns (for 133-MHz device) -- 7.5 ns (for 117-MHz device) -- 8.0 ns (for 100-MHz device) * Clock Enable (CEN) pin to suspend operation * Synchronous self-timed writes * Asynchronous Output Enable * Pb-Free 100 TQFP package * Burst Capability--linear or interleaved burst order * Low standby power
Functional Description[1]
The CY7C1353G is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353G is equipped with the advanced No Bus LatencyTM (NoBLTM) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by the two Byte Write Select (BW[A:B]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.
Logic Block Diagram
A0, A1, A MODE CLK CEN C CE ADV/LD C WRITE ADDRESS REGISTER ADDRESS REGISTER A1 D1 A0 D0 BURST LOGIC Q1 A1' A0' Q0
ADV/LD BWA BWB WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY
S E N S E A M P S
D A T A S T E E R I N G
O U T P U T B U F F E R S E
DQs DQPA DQPB
WE
OE CE1 CE2 CE3 ZZ
INPUT REGISTER READ LOGIC
E
SLEEP CONTROL
Note: 1.For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05515 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised October 22, 2004
PRELIMINARY
Selection Guide
Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 133 MHz 6.5 225 40 117 MHz 7.5 220 40
CY7C1353G
100 MHz 8.0 205 40 Unit ns mA mA
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Pin Configurations
100-lead TQFP
NC / 18M BWB BWA CE1 CE2 CE3 VDD VSS CEN CLK ADV/LD NC / 9M
WE
OE
NC
NC
A
A
A 82
100
99
94
91
98
97
96
95
93
92
90
89
88
87
86
85
84
83
NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
81
A
CY7C1353G
BYTE B
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC
BYTE A
A1
A0
NC
NC
VSS
VDD
NC / 72M
NC / 36M
MODE
A
A
A
A
A
A
A
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A
A
A
A
Page 2 of 13
PRELIMINARY
Pin Definitions (100-pin TQFP Package)
Name A0, A1, A BW[A:B] WE ADV/LD I/O Description
CY7C1353G
InputAddress Inputs used to select one of the 256K address locations. Sampled at the rising edge Synchronous of the CLK. A[1:0] are fed to the two-bit burst counter. InputByte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the Synchronous rising edge of CLK. InputWrite Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This Synchronous signal must be asserted LOW to initiate a write sequence. InputAdvance/Load Input. Used to advance the on-chip address counter or load a new address. When Synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW.
CLK CE1 CE2 CE3 OE
InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE2, and CE3 to select/deselect the device. InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE1 and CE3 to select/deselect the device. InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE1 and CE2 to select/deselect the device. InputOutput Enable, asynchronous input, active LOW. Combined with the synchronous logic block Asynchronous inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. InputClock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM. Synchronous When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. InputZZ "sleep" Input. This active HIGH input places the device in a non-time critical "sleep" condition Asynchronous with data integrity preserved. During normal operation, this pin can be connected to Vss or left floating. I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. I/OBidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write Synchronous sequences, DQP[A:B] is controlled by BWx correspondingly. Input Strap Pin MODE Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. Power supply for the I/O circuitry. Ground for the device. No Connects. Not Internally connected to the die. 9M,18M,36M and 72M are address expansion pins and are not internally connected to the die.
CEN
ZZ
DQs
DQP[A:B] MODE
VDD VDDQ VSS NC
Power Supply Power supply inputs to the core of the device. I/O Power Supply Ground -
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PRELIMINARY
Functional Overview
The CY7C1353G is a synchronous flow-through burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BW[A:B] can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE is active LOW. After the first clock of the read access, the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (Read/Write/Deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output will be tri-stated immediately. Burst Read Accesses The CY7C1353G has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enable inputs or WE. WE is latched at the
CY7C1353G
beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to the address bus is loaded into the Address Register. The write signals are latched into the Control Logic block. The data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs and DQP[A:B]. On the next clock rise the data presented to DQs and DQP[A:B] (or a subset for byte write operations, see truth table for details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled by BW[A:B] signals. The CY7C1353G provides byte write capability that is described in the truth table. Asserting the Write Enable input (WE) with the selected Byte Write Select input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1353G is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQP[A:B] inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs and DQP[A:B].are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1353G has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW[A:B] inputs must be driven in each cycle of the burst write, in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
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PRELIMINARY
Linear Burst Address Table (MODE = GND)
First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10
CY7C1353G
Interleaved Burst Address Table (MODE = Floating or VDD)
First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Snooze mode standby current Device operation to ZZ ZZ recovery time ZZ active to snooze current ZZ inactive to exit snooze current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 40 2tCYC Unit mA ns ns ns ns
Truth Table [2, 3, 4, 5, 6, 7, 8]
Operation Deselect Cycle Deselect Cycle Deselect Cycle Continue Deselect Cycle READ Cycle (Begin Burst) READ Cycle (Continue Burst) NOP/DUMMY READ (Begin Burst) DUMMY READ (Continue Burst) WRITE Cycle (Begin Burst) WRITE Cycle (Continue Burst) NOP/WRITE ABORT (Begin Burst) WRITE ABORT (Continue Burst) IGNORE CLOCK EDGE (Stall) SNOOZE MODE Address Used None None None None External Next External Next External Next None Next Current None CE1 H X X X L X L X L X L X X X CE2 X X L X H X H X H X H X X X CE3 X H X X L X L X L X L X X X ZZ L L L L L L L L L L L L L H ADV/LD L L L H L H L H L H L H X X WE X X X X H X H X L X L X X X BWX OE X X X X X X X X L L H H X X X X X X L L H H X X X X X X CEN L L L L L L L L L L L L H X CLK L->H L->H L->H L->H DQ tri-state tri-state tri-state tri-state
L->H Data Out (Q) L->H Data Out (Q) L->H L->H tri-state tri-state
L->H Data In (D) L->H Data In (D) L->H L->H L->H X tri-state tri-state - tri-state
Notes: 2.X ="Don't Care." H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see truth table for details. 3.Write is defined by BWX, and WE. See truth table for Read/Write. 4.When a write cycle is detected, all I/Os are tri-stated, even during byte writes. 5.The DQs and DQP[A:B] pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6.CEN = H, inserts wait states. 7.Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE. 8.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:B] = tri-state when OE is inactive or when the device is deselected, and DQs and DQP[A:B] = data when OE is active.
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PRELIMINARY
Partial Truth Table for Read/Write[2, 3, 9]
Function Read Write - No bytes written Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write All Bytes WE H L L L L BWA X H H H L
CY7C1353G
BWB X H H H L
Note: 9. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write will be done based on which byte write is active.
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PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +4.6V DC Voltage Applied to Outputs in tri-state ............................................ -0.5V to VDDQ + 0.5V DC Input Voltage....................................-0.5V to VDD + 0.5V
CY7C1353G
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Ambient Range Temperature (TA) Com'l Ind'l 0C to +70C -40C to +85C VDD VDDQ
3.3V - 5%/+10% 2.5V - 5% to VDD
Electrical Characteristics Over the Operating Range [10,11]
Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input HIGH Voltage Input LOW Voltage[10] Input LOW Voltage[10] Input Load Current (except ZZ and MODE) Input Current of MODE Input Current of ZZ IOZ IDD Output Leakage Current VDD Operating Supply Current VDDQ = 3.3V, VDD = Min., IOH = -4.0 mA VDDQ = 2.5V, VDD = Min., IOH = -1.0 mA VDDQ = 3.3V, VDD = Min., IOH = 8.0 mA VDDQ = 2.5V, VDD = Min., IOH = 1.0 mA VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V GND VI VDDQ Input = VSS Input = VDD Input = VSS Input = VDD GND VI VDD, Output Disabled VDD = Max., IOUT = 0 mA, f = fMAX= 1/tCYC 7.5-ns cycle, 133 MHz 8.5-ns cycle, 117 MHz 10-ns cycle, 100 MHz ISB1 Automatic CE Power-down Current--TTL Inputs VDD = Max, Device Deselected, 7.5-ns cycle, 133 MHz VIN VIH or VIN VIL, f = fMAX, 8.5-ns cycle, 117 MHz inputs switching 10-ns cycle, 100 MHz VDD = Max, Device Deselected, All speeds VIN VDD - 0.3V or VIN 0.3V, f = 0, inputs static VDD = Max, Device Deselected, 7.5-ns cycle, 133 MHz VIN VDDQ - 0.3V or VIN 0.3V, 8.5-ns cycle, 117 MHz f = fMAX, inputs switching 10-ns cycle, 100 MHz VDD = Max, Device Deselected, All speeds VIN VDD - 0.3V or VIN 0.3V, f = 0, inputs static -5 -5 30 5 225 220 205 90 85 80 40 2.0 1.7 -0.3 -0.3 -5 -30 5 Test Conditions Min. 3.135 2.375 2.4 2.0 0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 Max. 3.6 VDD Unit V V V V V V V V V V A A A A A A mA mA mA mA mA mA mA
ISB2
Automatic CE Power-down Current--CMOS Inputs Automatic CE Power-down Current--CMOS Inputs
ISB3
75 70 65 45
mA mA mA mA
ISB4
Automatic CE Power-down Current--TTL Inputs
Shaded areas contain advance information. Notes: 10.Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2). 11.TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200ms. During this time VIH < VDD and VDDQ < VDD.
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PRELIMINARY
Thermal Resistance[12]
Parameters JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51.
CY7C1353G
TQFP Typ. TBD TBD Unit C/W C/W
Capacitance[12]
Parameter CIN CCLOCK CI/O Description Input Capacitance Clock Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V VDDQ=3.3V Max. 5 5 5 Unit pF pF pF
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT Z0 = 50 3.3V OUTPUT RL = 50 5 pF R = 351
R = 317 ALL INPUT PULSES VDDQ 10% GND 1ns 90% 90% 10% 1ns
VT = 1.5V (a)
2.5V I/O Test Load
OUTPUT Z0 = 50
INCLUDING JIG AND SCOPE 2.5V
(b)
R = 1667 VDDQ 10% GND R =1538 1ns
(c)
ALL INPUT PULSES 90% 90% 10% 1ns
OUTPUT RL = 50 VT = 1.25V 5 pF INCLUDING JIG AND SCOPE
(a)
(b)
(c)
Switching Characteristics Over the Operating Range [17, 18]
133 MHz Parameter tPOWER Clock tCYC tCH tCL Output Times tCDV tDOH Data Output Valid After CLK Rise Data Output Hold After CLK Rise 2.0 6.5 2.0 7.5 2.0 8.0 ns ns Clock Cycle Time Clock HIGH Clock LOW 7.5 2.5 2.5 8.5 3.0 3.0 10 4.0 4.0 ns ns ns Description VDD(Typical) to the first Access[13] Min. 1 Max. 117 MHz Min. 1 Max. 100 MHz Min. 1 Max. Unit ms
Shaded areas contain advance information. Notes: 12.Tested initially and after any design or process changes that may affect these parameters. 13.This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above VDD minimum initially before a read or write operation can be initiated. 14.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 15.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve tri-state prior to Low-Z under the same system conditions. 16.This parameter is sampled and not 100% tested. 17.Timing reference level is 1.5V when VDDQ=3.3V and is 1.25V when VDDQ=2.5V. 18.Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
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PRELIMINARY
Switching Characteristics Over the Operating Range (continued)[17, 18]
133 MHz Parameter tCLZ tCHZ tOEV tOELZ tOEHZ Set-up Times tAS tALS tWES tCENS tDS tCES Hold Times tAH tALH tWEH tCENH tDH tCEH Address Hold After CLK Rise ADV/LD Hold after CLK Rise WE, BWX Hold After CLK Rise CEN Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Address Set-up Before CLK Rise ADV/LD Set-up Before CLK Rise WE, BWX Set-Up Before CLK Rise CEN Set-up Before CLK Rise Data Input Set-up Before CLK Rise Chip Enable Set-up Before CLK Rise 1.5 1.5 1.5 1.5 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 Clock to Low-Z Description
[14, 15, 16]
CY7C1353G
117 MHz Min. 0 3.5 3.5 3.5 3.5 0 3.5 3.5 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 0 3.5 Max. 100 MHz Min. 0 3.5 3.5 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min. 0
Max.
Clock to High-Z[14, 15, 16] OE LOW to Output Valid OE LOW to Output Low-Z
[14, 15, 16] [14, 15, 16]
0
OE HIGH to Output High-Z
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PRELIMINARY
Switching Waveforms
Read/Write Waveforms[19, 20, 21]
CY7C1353G
1 CLK
tCENS tCENH
2
tCYC
3
4
5
6
7
8
9
10
tCH
tCL
CEN
tCES tCEH
CE ADV/LD WE BW[A:B] ADDRESS
tAS
A1
tAH
A2
A3
tCDV tCLZ
A4
tDOH Q(A3) Q(A4) tOEHZ tOEV
A5
tCHZ
A6
A7
DQ
tDS
D(A1) tDH
D(A2)
D(A2+1)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
OE COMMAND
WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1)
tOELZ
tDOH
WRITE D(A5)
READ Q(A6)
WRITE D(A7)
DESELECT
DON'T CARE
UNDEFINED
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PRELIMINARY
Switching Waveforms
NOP, STALL and DESELECT Cycles[19, 20, 22]
1 CLK CEN CE ADV/LD WE BW[A:B] ADDRESS DQ COMMAND
WRITE D(A1)
CY7C1353G
2
3
4
5
6
7
8
9
10
A1
A2 D(A1)
READ Q(A2) STALL
A3 Q(A2)
READ Q(A3)
A4 Q(A3)
WRITE D(A4) STALL
A5
tCHZ
D(A4)
NOP READ Q(A5)
Q(A5)
tDOH DESELECT CONTINUE DESELECT
DON'T CARE
UNDEFINED
ZZ Mode Timing[23,24]
CLK
t ZZ t ZZREC
ZZ
t ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Notes: 19.For this waveform ZZ is tied low. 20.When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 21.Order of the Burst sequence is determined by the status of the MODE (0= Linear, 1= Interleaved). Burst operations are optional. 22.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle. 23.Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 24.DQs are in high-Z when exiting ZZ sleep mode.
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PRELIMINARY
Ordering Information
Speed (MHz) 133 133 117 117 100 100 Ordering Code CY7C1353G-133AXC CY7C1353G-133AXI CY7C1353G-117AXC CY7C1353G-117AXI CY7C1353G-100AXC CY7C1353G-100AXI Package Name A101 A101 A101 A101 A101 A101 Package Type
CY7C1353G
Operating Range Industrial Industrial Industrial
Lead-Free 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial Lead-Free 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Lead-Free 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Lead-Free 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Lead-Free 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial Lead-Free 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial
Shaded areas contain advance information. Please contain your local sales representative for more information on ordering these parts.
Package Diagrams
100-lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
ZBT is a trademark of Integrated Device Technology. NoBL and No Bus Latency are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05515 Rev. *A
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
Document History Page
Document Title: CY7C1353G 4-Mbit (256K x 18) Flow-through SRAM with NoBLTM Architecture Document Number: 38-05515 REV. ** *A ECN NO. 224363 288431 Issue Date
See ECN See ECN
CY7C1353G
Orig. of Change RKF VBL New data sheet
Description of Change Deleted 66 MHz Changed TQFP package in Ordering Information section to lead-free TQFP
Document #: 38-05515 Rev. *A
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